With the recent advancement in the field of high density information storage device, it has become a matter of special interest to develop an optical or electronic memory device through the implementation of a chalcogenide-based phase change material. By exploiting fast and reversible phase changes between the crystalline and amorphous states and their differences in optical characteristics or in electrical resistance, a means of information storage can be attained. For instance, the difference in their optical reflectance is utilized in rewritable CD and DVD optical disks, while phase change non-volatile memory and electrical probe-based memory exploit the difference in the electrical resistance between crystalline and amorphous states.
Specifically, phase change non-volatile memory devices named alternatively OUM (Ovonic Unified Memory), PRAM (Phase-change Random Access Memory), or CRAM (Chalcogenide Random Access Memory) have been actively researched for commercialization as viable substitutes for flash memory with DRAM-level performance.
In FIGS. 1a and 1b, two kinds of phase change non-volatile memory devices are presented.
Basically, they both have top electrodes 11, 11′ and bottom electrodes 12, 12′ for the input and output of electrical signals; memory areas 13, 13′ containing chalcogenide-based phase change materials; and insulating areas 14, 14′ for electrical and thermal insulation.
The difference between these two structures is that the memory device of FIG. 1b is further provided with a separate electrode 15′ for the joule-heating of the memory area 13′. On the other hand, the memory material itself is responsible for the joule-heating in FIG. 1a, the memory material being disposed in the central enclosed area 13.
The phase change memory device works by the following mechanism. When an electric voltage or current pulse is applied between the top and bottom electrodes, there takes place direct or indirect heating to melt the phase change material. At the end of the electric pulse, the melted phase change material is quenched to form an amorphous state, achieving information writing. This operation is called a reset operation. To erase this stored information, an electric pulse is applied to the amorphous phase change material such that suitable crystallization conditions in terms of, e.g. heating time and temperature, are met. Once crystallized, the stored information in the memory cell is erased. This operation is called a set operation.
The memory cell presents different electrical resistance depending on whether it is in a crystallized or amorphous state. The amorphous state exhibits a higher electrical resistance than the crystallized state. Therefore, by sensing the electrical resistance of a memory cell, stored binary information can be read.
Stoichiometric composition of a GeSbTe-based pseudo-binary material, (GeTe)x(Sb2Te3)1-x (x represents a mole fraction, 0<x<1) was developed as a practical phase change material capable of electrically switching between the amorphous and crystallized states in a reversible manner. Despite its merits as a phase change non-volatile memory material, the GeSbTe based material is disadvantageous in that it has a relatively high melting temperature of 600° C.˜700° C. This is problematic since such a high melting temperature requires more current and power for a reset operation of a phase change memory cell.
Shown in FIG. 2 is the dependency of the current level supplied from a transistor and that needed for a reset operation on the minimum feature size (F) or contact size (0.5 F). The dashed line in FIG. 2 indicates the current level of a transistor supplied to a phase change memory cell having 8 F2 DRAM cell structure as schematically shown in the inset. The solid line in FIG. 2 represents the change in the current level needed for a reset operation when the current density level is maintained at 100 mA/μm2, which is the value slightly smaller than the current density value estimated from the reset current level and contact size of an existing phase change memory proto-type (refer to the results of Intel/Ovonyx in ISSCC 2002 and Samsung Electronics in NVSMW 2003, the current density being 123.5 mA/μm2 and 138.9 mA/μm2, respectively).
As shown in FIG. 2, the current level supplied from the transistor cannot match the required reset current level until the feature size is reduced down to about 45 nm or smaller.
Reduction of the current level needed for a reset operation may be achieved by; lowering the melting temperature of the phase change material used in the memory cell; enhancing the generation/confinement of joule heat by way of changing the materials and the structure of the memory cell; or combining both.
In fact, substantial improvement may not be gained just by lowering the melting temperature of the memory material; for example, the drastic reduction of the melting temperature from 900 K to 450 K would save only 50% of the electric power. Accordingly, a combined approach is in need.
Another technical issue of critical importance in the development of a successful phase change memory device, is to reduce the thermal interference between memory cells so as to prevent a possible crystallization of the memory material in the amorphous state by the heat produced in adjacent cells during the reset process. A fundamental approach to this problem would be to lower the melting temperature of the memory material while raising the crystallization temperature thereof.
In summary, in order to reduce the power consumption and thermal interference between cells, there exists a need to develop a memory material having a low melting temperature and a high crystallization temperature together with the optimal characteristics of joule heat generation and confinement.